Zeni EDA Software Tools

SPICE Simulator | SPICE-Verilog Mixed Simulation

Schematic SPICE Physical Design Verification Parasitic Extraction Signal Integrity

HSPICE Compatible SPICE Simulator

Mixed-mode simulator, superior convergence and speed

Convergence is often a problem with many simulators especially in power electronics. This is because the wide range of currents, voltages and conductances present in power circuits stretches the precision of the underlying algorithms. Many other products have to be coaxed into completing such designs by requiring the user to experiment with various option settings. This is rarely necessary with our SPICE simulator and is the result of over 15 years of development on the core algorithms and model equations along with real world experience in simulator use.

Verilog-HDL and SPICE Mixed Simulation

The Verilog-HDL feature provides the ability to simulate Verilog digital designs included in analog circuits. This SPICE-Verilog co-simulation feature is very useful when simulating large designs or at the full chip level, and provides significant performance and accuracy improvements over traditional simulations running in SPICE or Verilog separately.

Verilog-A Modelling Language

Verilog-A is a language for defining analog models; it is suitable for defining behavioural models with a high level of abstraction as well as highly detailed models for semiconductor devices.

S-Parameter AC Lookup Table

The AC Table device implements a circuit device that is defined by a s-parameter vs frequency lookup table and works in the small signal analysis modes. The lookup table for this device is defined by a file using the industry standard 'Touchstone' format.

Extended sweep modes

Our SPICE simulator has six sweep modes applicable to DC, AC, Noise and Transfer Function analyses whereas SPICE has just one for each. For example you can sweep a voltage source at a constant frequency in AC analysis with our SPICE simulator but not other SPICE programs.

Real time noise analysis

Applies noise in transient analysis. This unique feature makes it possible to analyse noise in oscillators and sampled data systems.

Transient analysis snapshots

Stores the circuit state at any point during a transient run. Result can be used to initialise an AC analysis. Useful for investigating the stability of circuits in operating conditions that cannot be obtained using a DC analysis.

Model support for IC design

Includes, BSIM3, BSIM4, MOS9, MOS11, PSP, Mextram, Hicum, EKV and VBIC models, schematic support for L/W editing.

HSPICE model file compatible

Includes: support for HSPICE syntax for parameter expressions; .LIB/.ENDL support; process binning; .GLOBAL; LEVEL 49 and LEVEL 53 BSIM3 model parameters.

Fast Monte Carlo analysis

Our SPICE simulator has possibly the fastest Monte Carlo analysis of any PC based product. Unlike other simulators, our SPICE simulator's Monte Carlo feature is built into the simulator core making it possible to use algorithms that avoid unnecessary repetition.

Sophisticated tolerance specification

As well as high performance, our SPICE simulator also provides sophisticated tolerance specification allowing simple cases to be setup quickly while providing the flexibility needed for large IC designs. Our SPICE simulator also features a facility to create histograms of analysis data using a wide range of goal functions.

Multi-step analysis

Repeats an analysis while varying some circuit variable using one of six modes.

Safe Operating Area (SOA) analysis

Displays violations of voltage, current or power limits as the simulation runs.

Non-linear magnetics with support for air gaps

Two models are available: the Jiles-Atherton hysteresis model and a simple non-hysteresis model.

Power models

Built-in IGBT model compatible with PSpice.
Full support for Infineon physics based models including CoolMos and Optimos devices.
New soft recovery diode model. Includes parameter extraction facility to create models from data sheet values.

Transient restart

Transient analysis can be restarted after the stop time has been reached. Useful when a circuit takes longer to settle than originally expected.

Email us with any other questions you may have: info(at)zeni-eda.com