Zeni EDA Software Tools

Physical Verification Tools | DRC ERC LVS

Schematic SPICE Physical Design Verification Parasitic Extraction Signal Integrity

The Zeni Veri tools assist customers to verify the physical and electrical integrity of Integrated Circuits. They offer both flat and hierarchical design verification methods. Flat Veri is best for verifying small to large databases, hierarchical Veri is best for verifying large hierarchical databases. The Zeni Veri tools operate on rule files which support other industry standard verification tools. The figure below shows flat Zeni Veri tool flow.

Layout Verification

Zeni DRC

The main objective of Design Rule Check (DRC) is to achieve a high overall die yield and reliability for the integrated circuit being designed. Zeni DRC is a full-featured design rule checking tool and an important part of Zeni’s complete suite of physical verification tools. It provides designers with the capability to check and identify design rule errors, and achieve the full correctness of IC layout. Not only is Zeni DRC fast, it also supports three running modes, offering customers great flexibility to perform design rule checking: Online Mode, Batch Mode and Interactive Mode. Online mode enables designers to check for drc errors and remove any violations while working on the layout.

Zeni DRC’s command file is easy to write, and fully compatible with Dracula format. It supports importing error files from third-party verification tools such as Dracula and Calibre. Zeni DRC has an easy-to-use interface. Designers can set breakpoints at any time and rerun the verification process. Zeni DRC can take GDS or Zeni’s internal layout format as design input, and generate output in GDS, ASCII or binary format. All these features give customers unparalleled capability to efficiently locate and eliminate design rule errors, and greatly reduce the time spent on layout design.

DRC Software

DRC Tools


Zeni HDRC performs checks on layout geometries in a fully hierarchical manner. With the dramatic increase in the size and scale of today's ICs, flat verification applications cannot meet the perfoemance requirements on large designs. Unlike flat verification applications that completely flatten the input database, Zeni HDRC maintains the database hierarchy and exploits this hierarchy to reduce processing time, memory usage and DRC error counts. On most large designs, significant speed improvements can be realized by using Zeni HDRC.

Zeni HDRC supports an extensive set of design rules, including conjunctive rules. The DRC commands are technology independent, and include logical operation commands, sizing commands and spacing commands. Zeni HDRC can also accepts industry standard hierarchical command files. These can be compiled and directly executed, without any changes or translations.

Hierarchical DRC

Zeni ERC

Zeni ERC can check the design layout for multiple types of electrical rule violations, including open circuits, floating nodes, invalid devices, improper VDD/GND connections, and others. It is especially useful in finding shorts between global signals, and makes debugging these errors quite convenient.

Zeni ERC's command file is fully compatible with Dracula format. Like the other VERI tools, it can be run in online mode, batch mode, or interactive mode. Zeni ERC can run independently, or with Zeni LVS.

ERC Software

ERC Tools

ERC Flow

Zeni LVS

Layout versus Schematic (LVS) is an essential part of the physical verification process, ensuring correctness of the design layout. Zeni LVS compares the drawn layout geometries against the schematic, using the corresponding CDL or SPICE netlist files. It compares the connectivity at the device level, and all device subtypes and device parameters can be compared and matched. It can also be used for LVL and SVS purposes. Zeni LVS's command file is fully compatible with industry standard command file formats.

Zeni's unique graphical debug tool, LDX, creates a schematic representation of the circuit that is equivalent to the physical layout. This allows the original schematic to be compared side-by-side with the "layout schematic" and facilitate easy debuging during LVS.

LVS Tools

LVS Software

Email us with any other questions you may have: info(at)zeni-eda.com

1: Dracula is a registered trademark of Cadence Design Systems, Inc.
2: Calibre is a registered trademark of Mentor Graphics Corporation
3: Hercules is a registered trademark of Synopsys, Inc.